A Low-Cost Multi-Sized HEVC Core Transform Using Time-Multiplexed DCT ‎Architectures

Document Type : Research paper

Authors

1 Department of Electrical Engineering, Faculty of Engineering, Islamic Azad University, Saveh Branch, Saveh, Iran

2 ‎Department of Computer Engineering, Faculty of Engineering, Islamic Azad University, Saveh Branch, Saveh, Iran ‎

Abstract

High Efficiency Video Coding (HEVC) is one of the latest coding standards targeting high-resolution video contents. Due to the high complexity of the existing hardware implementation, this paper presents the low-cost and efficient DCT architectures for HEVC, which are able to perform DCT operation of multiple transform sizes in a single unified architecture. Our objective is to reuse the hardware resources in a DCT architectures using configurable constant multipliers as well as reducing the hardware cost and trading off between hardware complexity and efficiency. We propose three different shift-and-add units with different hardware cost and throughput. The main advantage of the proposed architectures over the existing architectures is a lower hardware and it can also perform DCT transform of different transform units which is available in HEVC standard. The experimental results over 90-nm technology show that the proposed 2D-DCT architecture #1 archives the lowest hardware cost amongst the rest of the architectures with around 57% reduction in gate count, on average. The unfolded 2D-DCT architectures #2 and #3 offer the moderate reduction in gate count around 47%, on average, with a moderate throughput. Apart from architectures #1, #2, and #3, we also develop a reusable architecture by adding an extra ( )-point DCT alongside the main DCT.

Keywords

References

  1. Rao, D. Kim, and J. Hwang, “Video coding standards”, The Netherlands: Springer, pp. 51–97, 2014.
  2. Masera, M. Martina, and G. Masera, “Adaptive approximated DCT architectures for HEVC”, IEEE Trans. Circuits Syst. Video Tech., vol. 27, no. 12, pp. 2714-25, 2017.
  3. Shabani, S. Timarchi, and H. Mahdavi, “Power and area efficient CORDIC-Based DCT using direct realization of decomposed matrix”, Microelectron. J., vol. 91, pp. 11-21, 2019.
  4. Seyed et al., “Analysis and synthesis of facial expressions by feature-points tracking and deformable model”, 2007.
  5. Abadpour and S. Kasaei, “A novel color image compression method using eigenimages”, J. Iran. Assoc. Electr. Electron. Eng., vol. 5, no. 2, pp. 49-57, 2008.
  6. Mahdavipour, “Image de-noising and micro crack detection of solar cells”, J. Iran. Assoc. Electr. Electron. Eng., vol. 14, no. 4, pp. 55-61, 2018.
  7. Shabani and S. Timarchi, “Low-power DCT-based compressor for wireless capsule endoscopy”, Signal Proc.: Image Commun., vol. 59, pp. 83-95, 2017.
  8. Saidi et al., “A new adaptive image steganography scheme based on DCT and chaotic map”, Multimedia Tools Appl., vol. 76, no. 11, pp. 13493-510, 2017.
  9. Budagavi et al., “Core transform design in the high efficiency video coding (HEVC) Standard”, IEEE J. Selected Top. Signal Proc., vol. 7, pp. 1029-41, 2013.
  10. . McCann et al., “High efficiency video coding (HEVC) test model 8 (HM 8) encoder description”, JCT-VC Documents , Sweden, 2012.
  11. Budagavi and V. Sze, “Unified forward+inverse transform architecture for HEVC”, Proc. Int. Conf. Image Proc., 2012.
  12. Park and P. Meher, “Flexible integer DCT architectures for HEVC”, Proc. IEEE Int. Symp. Circuits Syst., 2013.
  13. Meher et al., “Efficient integer DCT architectures for HEVC”, IEEE Trans. Circuits Syst. Video Tech., vol. 24, no. 1, pp. 168-78, 2014.
  14. Darji and R. Makwana, “High-performance multiplierless DCT architecture for HEVC”, 19th Int. Symp. VLSI Des. Test, 2015.
  15. Goebel et al., “An HEVC multi-size DCT hardware with constant throughput and supporting heterogeneous CUs”, Proc. IEEE Int. Symp. Circuits Syst., 2016.
  16. Ahmed, M. Shahid, and A. Rehman, “N point DCT VLSI architecture for emerging HEVC standard”, VLSI Des., 2012.
  17. Masera, G. Masera, and M. Martina, “An area-efficient variable-size fixed-point DCT architecture for HEVC encoding”, IEEE Trans. Circuits Syst. Video Tech., vol. 30, no. 1, pp. 232-42, 2020.
  18. Shen et al., “A unified 4/8/16/32-point integer IDCT architecture for multiple video coding standards”, Proc. IEEE Int. Conf. Multimedia Expo., 2012.
  19. Sun et al., “A low-cost VLSI architecture of multiple-Size IDCT for H.265/HEVC”, IEICE Trans. Fundamentals Electron. Commun. Comput. Sci., vol. E97A, no. 12, pp. 2467-76, 2014.
  20. Chatterjee and K. Sarawadekar, “WHT and matrix decomposition-based approximated IDCT architecture for HEVC”, IEEE Trans. Circuits Syst. II: Express Briefs, vol. 66, no. 6, pp. 1043-47, 2019.
  21. Chatterjee and K. Sarawadekar, “An optimized architecture of HEVC core transform using real-valued DCT coefficients”, IEEE Trans. Circuits Syst. II: Express Briefs, vol. 65, no. 12, pp. 2052-6, 2018.
  22. Pratt, J. Kane, and H. Andrews, “Hadamard transform image coding”, Proc. IEEE, vol. 57, pp. 58-68, 1969.
  23. Chatterjee and K. Sarawadekar, “Approximated core transform architectures for HEVC using WHT-based decomposition method”, IEEE Trans. Circuits Syst. I: Reg. Pap., vol. 66, no. 11, pp. 4296-308, 2019.
  24. Fralick, “A fast computational algorithm for the discrete cosine transform”, IEEE Trans. Commun., vol. 25, no. 9, pp. 1004-9, 1977.
  25. Voronenko and M. Püschel, “Multiplierless multiple constant multiplication”, ACM Trans. Algorithms, vol. 3, no. 2, 2007.
  26. Hassanzadeh and A. Shabani, “Low power parallel prefix adder design using two phase adiabatic logic”, J. Electr. Electron. Eng., vol. 3, no. 6, p. 181, 2015.
  27. Tummeltshammer, J. Hoe, and M. Puschel, “Time-multiplexed multiple-constant multiplication”, IEEE Trans. Comp. Aided Des. Integrated Circuits Syst., vol. 26, no. 9, pp. 1551-63, 2007.
  28. Zhao, T. Onoye, and T. Song, “High-performance multiplierless transform architecture for HEVC”, Proc. IEEE Int. Symp. Circuits Syst., pp. 1668-71, 2013.
  29. Kalali, A. Mert, and I. Hamzaoglu, “A computation and energy reduction technique for HEVC Discrete Cosine Transform”, IEEE Trans. Consumer Electron., vol. 62, no. 2, pp. 166-74, 2016.
  30. Bossen and K. Sühring, “Joint collaborative team on video coding (JCT-VC) of ITU-T SG16 WP3 and ISO/IEC JTC1/SC29/WG11”, 2015.
Journal of Operation and Automation in Power Engineering
Volume 10, Issue 2
August 2022
Pages 143-154

Files

History

  • Receive Date: 19 July 2021
  • Revise Date: 28 September 2021
  • Accept Date: 14 October 2021
  • First Publish Date: 21 October 2021

Share

How to cite

Statistics